The present invention relates to integrated circuits, and more particularly to CMOS integrated circuits.
In the prior art of bulk CMOS devices, one of the major limitations on scaling the device into smaller sizes is the necessity to avoid latch-up. "Latch-up" is the self-sustaining current flow through the pnpn thyristor defined by a p+ source/drain region, the n-type tank, the p-type well. and an n+ source/drain region. To avoid latch-up, it is necessary to specify minimum separations between p+ and n+ which are many times the minimum geometry of the device; for example, a one micron CMOS device might have five micron or larger n+ to p+ spacing rules. This large spacing is a major limitation on area efficiency of VLSI CMOS integrated circuits.
One way which has been suggested to reduce the spacing requirements of n+ to p+ spacing is to make one or both types of transistors with their active areas in recrystallized polysilicon. However, such devices tend to be quite difficult to manufacture reproducibly. In particular, manufacturing can require many difficult nonstandard steps, and channel mobility may be variable.
A third criterion in development of CMOS devices (besides density and speed) is resistance to single event upset (SEU). That is, integrated circuits will always be exposed to a certain background radiation level, and, as the circuits are scaled to smaller and smaller geometries, many conventional processes have become more sensitive to stray carriers caused by alpha particles. That is, an alpha particle striking a silicon substrate will typically release plural electron-hole pairs, and the fields near the source/drain junctions of active devices may collect enough charge from one such incident to cause reversal of the electrical state of a node, that is an electrical error may be introduced into the logic circuit by the single event upset.
The present invention provides a new device structure and process for making it, and meets needs which were not satisfied by the prior art. In particular. the present invention provides a CMOS device having high speed, low leakage current, high resistance to single event upset, and permits closer spacing of p+ to n+ regions than was permitted in the prior art. Moreover, the spacing may be made such that the minimum separation across a field isolation region between N Channel and P Channel devices is not more than 3/2 times the minimum separation across field isolation regions between any two N Channel devices.
The present invention provides an insulated gate field-effect transistor having a crystalline channel and having sources and drains which are almost completely oxide isolated. These oxide isolated "source/drain" regions are formed by etching a recess in silicon, lining the etched recess with oxide, and backfilling with polysilicon. A short isotropic oxide etch, followed by a polysilicon filament deposition, then makes electrical contact between the oxide-isolated source/drain-contact regions and the channel region of the active device. Use of sidewall nitride filaments on the gate permits the silicon etch step to be self-aligned.
The dopants in these "source/drain" regions will outdiffuse through the small area of contact with crystalline silicon, near the channel area, to form very small diffusions which function electrically as the source/drain regions..sup.1 Thus, the critical p+ to n+ separation is not defined by the shortest distance between adjacent recessed source/drain regions, but instead is defined by the minimum distance along the path from the small p+ outdiffusion at the edge of the channel region of one transistor, down under the recessed p+ source/drain-contact, underneath the field oxide, underneath the n+ recessed source/drain region, and up to the small n-type outdiffusion at the edge of the channel of an NMOS device. This means that the effective p+ to n+ separation is much larger than that which the circuit designers layout would appear to indicate; in fact, it may even be possible to remove p+ to n+ separation as a separate design rule. FNT .sup.1 A note regarding terminology: the (mostly) oxide encapsulated heavily doped regions self-aligned to the gate which are taught by preferred embodiments of the present invention occupy almost the same position in the transistor structure (particularly in a horizontal view of the transistor) as the source/drain regions of prior art MOS devices, and these structures are therefore referred to, in quotes, as "source/drain" regions. However, as noted, these "source/drain" regions are not the electrically effective source/drain regions, i.e. majority carriers are not emitted directly from these oxide encapsulated heavily doped regions into the channel: the electrically effective source/drain regions are the relatively small diffusions formed by outdiffusion at the small areas where the oxide-isolated heavily doped polycrystalline regions adjoin crystalline silicon near the channel area. For clarity, the novel "source/drain" structures provided by the present invention will usually be referred to as source/drain-contact regions, but it should be noted that these source/drain-contact regions do not merely serve as contacts, but also can provide conductive diffusions, and/or serve other purposes. Contact is made to the source/drain contact regions in essentially the same ways as contact would be made to source/drain regions of prior art MOS devices.
Another key advantage of the present invention is the resistance to single event upset. Since the source/drain junctions are almost completely oxide isolated, the area per device which is able to collect charge is much smaller. This means that the fraction of single-particle absorptions which occur in a sufficiently favorable location for the generated charge to be collected and disturb the state of an electrical node will be substantially smaller.
Another major advantage of the present invention is improved control of the carrier mobility. Many silicon on insulator technologies form active device channels in deposited and annealed silicon, and consequently suffer from low or irreproducible mobility. Unlike such technologies, the present invention provides devices having their channels in grown bulk silicon which has not been exposed to damage from heavy implanting. Thus, the high mobility and low defect density of grown crystal silicon provide good transistor qualities for the present invention, while still obtaining many of the advantages of silicon-on-insulator devices.
The present invention does provide a device with a fairly sharp curvature on the electrically active source/drain junctions. However, since these diffusions are formed by outdiffusion from a compact source (as opposed to the diffuse source provided, in conventional technology, by the as-implanted source/drain dopants), the divergence of the doping density is larger for a given diffusion length (i.e. the integral of .sqroot.Dt, which is determined by the thermal characteristics of the complete set of processing conditions used) than in the prior art. This naturally produces a graded drain effect. Moreover, if desired, formation of source/drain-contact regions and source/drain diffusions according to the present invention can be combined with a lightly doped drain implant (performed before the gate sidewall filament deposition and silicon recess etch steps). Alternatively, if desired, formation of source/drain-contact regions and source/drain diffusions according to the present invention can be performed using two species of n-type dopants (e.g. both phosphorus and arsenic) to provide a graded doping density due to differential outdiffusion. Thus, yet another advantage of the present invention is that hot-electron effects can be minimized without introducing series resistance into the device electrical characteristics.
Another advantage of the present invention is that an additional extremely heavy channel stop implant can be made into the recess etched for the source/drain-contact regions. This provides further improved isolation..sup.2 It should be noted that the improved isolation is not merely improved between tanks (i.e. improved isolation between PMOS devices and adjacent NMOS devices), but is also improved between moats (i.e. between NMOS devices and other adjacent NMOS devices). In either case, the spacing between active diffusions in silicon is increased for the same patterned geometries, since the buried oxide which underlies the source/drain-contact regions acts as an extension of the field isolation region. Moreover, as noted, an additional very heavy channel stop implant can be made into the silicon under the buried oxide for improved isolation without any encroachment problems. FNT .sup.2 Note that this improved isolation is not isotropic: parasitic/leakage current paths which go under the source/drain-contact regions will be better controlled by this additional dose, but those which go in other directions will not. At the side of the gate, where the gate line crosses from the moat (the active device area) onto the field isolation region, the source/drain outdiffusions will extend approximately to the edge of the field isolation region. Thus, parasitic/leakage current paths which begin from the side of the gate will not in general be as well controlled by this additional dose as other leakage paths will be.
The field isolation preferably used for the present invention is not necessarily LOCOS isolation, but could instead be MF.sup.3 R (SWAMI) or other process which provides field isolation regions having approximately vertical sidewalls. Some of the self-aligned process embodiments of the present invention may produce a conductive ring around the surface of the oxide isolated source/drain-contact regions, and use of an isolation technology which does not produce highly tapered edges to the field isolation region may be desirable to avoid connecting the source/drain-contact regions to substrate at other locations except at the edge of an active device channel. That is, the isotropic oxide etch which permits the source/drain contact regions to contact the silicon near the channel should not be permitted to go deeply enough to permit contact to be made to the silicon underneath the field oxide. If the field isolation technology used is one (like MF.sup.3 R (SWAMI)) which provides a fairly steep slope at the field oxide to silicon lateral interface, this may not be a significant process constraint, but in other technologies this must be considered. Note also that it is preferable that the isolation technology used should provide field isolation regions which are at least somewhat recessed: for example, direct moat isolation would be substantially less preferable than LOCOS.
A further advantage of the present invention in reducing latch-up susceptibility is that, because most of the area of the source/drain junctions is effectively oxide isolated from the substrate, current regeneration effects (due to a reduction of junction barrier due to charge injection) can only occur at the very small electrically active source/drain area where the oxide isolated source/drain-contact region borders on the channel. That is, this junction in the parasitic thyristor is not only farther removed from the other junctions in the current thyristor, it is also smaller, which further reduces the current gain of the parasitic thyristor, as is desirable. Another way to consider this advantage is that the susceptibility to latch-up is reduced because the effective moat area (active device area) is reduced for a given patterned geometry.
The present invention also has the very important advantage of reduced short channel effects. The junction depth which determines short channel effects in the present invention is determined by the degree of undercut used to connect the oxide-isolated source/drain-contact regions to the bulk silicon, and by the integrated .sqroot.Dt (i.e. the diffusion length) of the outdiffusion into the bulk silicon. Using the present invention, this depth can be reduced to as little as 0.1 microns, as compared to the typical value of 0.15 to 0.25 microns for otherwise comparable advanced devices. The reduced junction depth permitted by the present invention can reduce various undesirable short channel effects, such as subthreshold leakage, V.sub.T shift, drain induced barrier lowering and current multiplication, and punchthrough. Drain induced barrier lowering and punchthrough are greatly reduced because the embedded oxide layer blocks collection of minority carriers generated by impact ionization near the drain and also reduces the electric field intensity along most of the source/drain boundary area (including both the electrically effective source/drain regions and the source/drain-contact regions).
A further advantage of the present invention is the reduced source/drain sheet resistance. The present invention differs from the prior art in that the depth of the source/drain-contact regions, and the effective junction depth associated with channel conductance, can be independently controlled. That is, sheet resistance of a thin layer is equal to resistivity .rho. divided by the film thickness. Since the resistivity of silicon cannot be much increased by doping beyond a certain point, the sheet resistance of source/drain diffusions in the prior art (disregarding any contribution from silicides or self-aligned tungsten or other surface shunting layer) can only be reduced by increasing the depth of the source/drain regions. However, increasing the depth of the source/drain regions has many side effects, and many of them are undesirable. One way of using this advantage is that the depth of the oxide isolated source/drain-contact regions can be increased as compared to conventional CMOS, thereby reducing the source/drain sheet resistance. Moreover, the source/drain-contact regions can be doped to saturation by very heavy implant doses. This means that the sheet resistance of these junctions can be much smaller than for conventional devices of comparable geometries. This means that speed of the device is improved, and that the utility of the source/drain-contact regions as interconnects is improved.
It should be noted that the presently preferred embodiments of the present invention relate to CMOS, but the present invention can also be used for NMOS devices, or even for PMOS devices.
A further advantage of the present invention is that it can be combined with a conventional self-aligned direct-react siliciding process, to silicide the surfaces of the gate and source/drain-contact regions, and/or to provide titanium nitride local interconnects, if desired.
In fact, the present invention is particularly advantageous in connection with processes for silicidation and/or local interconnect which create a surface layer which is able to absorb dopants from silicon. (For example, this is a potential problem with direct-react TiSi.sub.2 /TiN silicidation/local interconnect processes.) In conventional use of processes of this type, this absorption of dopants (together with consumption of silicon by the silicidation reaction) will make the source/drain diffusions more shallow, and may even make them so shallow that spiking (i.e. shorting from the contacts to the underlying substrate) occurs. Another potential problem with conventional processes of this type is contact resistance: if the silicide depletes source/drain dopants excessively, it can become difficult to form an ohmic contact with a low specific contact resistance. Another potential problem with conventional processes of this type is hot electron generation at the silicide corner nearest the gate, if too much of the voltage drop appears here. In embodiments of the present invention, since the depth of the source/drain-contact region can be made much greater than the depth of a conventional source/drain diffusion of comparable minimum lateral dimension, a larger total dose of dopants can be used at the source/drain implanting stage, to resist dopant depletion. Moreover, since the diffusivity of polysilicon is much higher than that of crystalline silicon, the dopant concentration will more readily equilibrate within the source/drain-contact region, so that the local depletion effects which can lead to high contact resistance are also avoided. Thus, the present invention, when combined with processes for silicidation and/or local interconnect which create a surface layer which is able to absorb dopants from silicon, provides advantages of improved resistance to spiking, improved specific contact resistance, and improved resistance to hot carrier effects.
Yet another advantage of the present invention is that the parasitic capacitance of the source/drain-contact regions will (for a given geometry and depth) be less than that of the source/drain regions used in the prior art. This reduction in parasitic capacitance will often translate directly into greater speed for the electrical circuits including devices according to the present invention.
In a further class of alternative embodiments of the invention, the oxide isolated source/drain-contact regions are not made of polysilicon at all, but are made of metal. That is, after the oxide-isolated recesses are formed, metal is deposited (preferably conformally) and planarized to fill the surface of the source/drain-contact recess. The oxide is then undercut, and conformal polysilicon deposition performed to electrically connect the oxide-isolated source/drain-contact regions to the substrate.
According to the present invention there is provided: A process for fabricating integrated circuits, comprising the steps of: providing a substrate having a monocrystalline upper portion: providing field isolation regions in predetermined locations in monocrystalline upper portion to define active device locations therebetween; forming insulated gate lines over predetermined locations including predetermined portions of said active device areas, said insulated gate lines defining transistor channels in portions of said active device areas; forming sidewall filaments on said gate lines; etching, to approximately a predetermined depth, areas of said monocrystalline upper portion of said silicon that are not covered by said gate lines, by said field isolation, nor by said sidewall filaments on said gate lines, to form a source/drain-contact recess; forming a dielectric conformally on bottoms and sidewalls of said recess; filling said source/drain-contact recesses with a conductive material; etching back said conformally formed dielectric from around said source/drain-contact recesses to produce a groove surrounding the surface of said source/drain-contact recesses, and refilling said groove with a filament of conductive material; and heating said substrate to cause outdiffusion of dopants from said isolated source/drain-contact regions, to create a plurality of source/drain diffusions connecting said source/drain contact regions to corresponding ones of said transistor channel regions.
According to the present invention there is also provided: An integrated circuit including insulated gate field effect transistor active devices, comprising: a substrate having a monocrystalline silicon upper portion; field isolation regions surrounding and defining a plurality of active device regions; a plurality of conductive gate lines crossing over said active device regions in predetermined locations to define transistor channels thereunder, said gate lines being insulated from said transistor channels; a plurality of source/drain-contact regions each comprising a body of conductive material recessed into said substrate and partially isolated therefrom by a conformal dielectric layer: wherein some upper portions of said source/drain-contact regions are connected to said substrate at locations adjacent to said channel region also containing source/drain outdiffusions therein connecting ones of said source/drain-contact regions to adjacent ones of said channel regions.